CPLD VS FPGA – All you need to know

Custom digital circuits can be implemented by engineers using two types of programmable logic devices: Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs).

They both provide digital systems with flexibility and quick development. Each is better suited for specific applications due to a few significant distinctions between the two, though.

Among new engineers and FPGA novices, one of the most frequent queries is “Should I use FPGA or CPLD?” The features that distinguish these two distinct logic devices from one another are different.

That being said, let us put an end to this discussion and make things clear: what distinguishes CPLD from FPGA?

This article aims to clarify some of the differences between them and provide some insight into the topic of which one to employ.

What is CPLD?

A single chip that has several SPLD (Simple Programmable Logic Device) types of blocks is called a CPLD (Complex Programming Logic Device).

It makes use of several PAL-like blocks and programmable connector lines; the distinction between PAL and PLA. 

The PAL consists of an array of programmable AND gates followed by fixed OR gates.

These PAL-like blocks are connected to a few input/output pins and can be programmed using the programming switches that are situated both vertically and horizontally about the interconnection wires.

What is FPGA?

The reason FPGAs (Field Programmable Gate Arrays) have the name is because they are constructed similarly to Application Specific Integrated Circuits or gate arrays. The structure is designed as a reversible circuit with a matrix of gate array logic.

Because of the internal circuitry’s connectivity, the FPGA’s setup affects the hardware through software.

Since processors and FPGA operate in parallel, they do not demand the same resources, which allows for the improvement of one application’s performance without compromising the other.

It also makes it possible to run several control loops at different speeds.

Unlike printed circuit boards (PCBs) that are hardwired, FPGAs can reconfigure their whole internal circuitry, allowing for hardware reconfiguration when the hardware is deployed. As specialized hardware, the FPGA circuits are dependable.

History and milestone of FPGA & CPLD

Year 1981- The patent application, titled Semiconductor Memory Device and Methods for Manufacturing the Same, was made on November 13th, 1981 by Fujio Masuoka and Hisakazu Lizuka. It was approved on July 23rd, 1985.

The invention of what is now known as Flash memory allowed for advancements over the previously developed EEPROM, as this patent details.

Year 1985 – Xilinx released the XC2064, the first FPGA, in 1985. The Look Up Tables (LUT) of the FPGA are composed of SRA and are connected by interconnects.

These LUTs can be programmed by the user, which was a groundbreaking development that made it possible for engineers to reprogram logic chips on the spot. Even now, Xilinx remains a significant player in the FPGA industry.

Year 1988 – Altera was responsible for PAL technology’s major advancement. The Complex Programmable Logic gadget (CPLD) was a novel gadget developed by Altera in the middle of the 1980s.

The MAX5000 device, which debuted in 1988, was Altera’s first CPLD. Blocks of the PAL type with connections between them make up the CPLDs.

CPLD Architecture & its working:

CPLD Architecture & Components

The AND plane in CPLD function blocks is capable of accepting inputs from I/O blocks, function blocks, or replies from other function blocks within the same block. After that, the terms are added to the OR array and chosen with the aid of a sizable multiplexer.

A timed flip-flop can be used to transport the MUX result out of the block directly or indirectly. Additional logic, such as a master reset signal, a choosable exclusive OR, and the capacity to program the polarity at different stages, can also be added to this functional block.

• Function block: An AND plane in a CPLD function block can accept inputs from other function blocks, I/O blocks, or even the function block’s own response. Once the terms are added to the OR array, they are chosen using a huge multiplexer.
• The MUX’s output can be moved out of the block directly or via a timed flip-flop. Further logic, including a master reset signal, a selectable exclusive OR, and the capacity to program the polarity incrementally, may also be included in this functional block.
• Interconnect: The interconnect of a CPLD is a large matrix of programmable switches that regulate the flow of signals between different parts of the device.
• Input/Output blocks: Using the input/output blocks, signals with the appropriate voltage and current levels are transmitted to the CPLD pins. It permits the removal of delays, the shortening of the device’s idle time need, and the inclusion of additional resources.

How does CPLD Work?

CPLD is a programming technology that produces extremely dense, quick, and energy-efficient programmable logic devices by utilizing CMOS EPROM, EEPROM, flash memory, and SRAM programming technologies.

They are enormous and have comparatively complicated structures, classed as large-scale integrated circuits.

A custom printed logic device, or CPLD, is a type of digital integrated circuit that lets users design custom logic circuits to fit their needs.

The primary method of design involves implementing the intended digital system using the hardware description language and integrated development software platform, downloading the code to the target chip via a download cable (a process known as “in-system” programming), and creating the corresponding target file.

FPGA Architecture & its working:

FPGA Architecture & Components

The heterogeneous compute platforms of FPGAs include programmable fabric, DSP slices, block RAMs, and PCI Express compatibility.

These compute resources allow parallelism and pipelining of applications throughout the platform because they can all be accessed simultaneously.

The fundamental components of an FPGA are memory, programmable interconnects, and logic units. Every manufacturer places these blocks differently.

FPGAs can be classified into three groups based on their internal block arrangement:

Symmetrical arrays

The logic components, also known as CLBs, are arranged in a matrix’s rows and columns with connections established between them.

This symmetrical matrix is surrounded by I/O blocks that link it to the external environment. Each CLB consists of an n-input Lookup table and two programmable flip-flops.

I/O blocks also regulate functions like output transition speed and tristate control. A routing path is created using interconnects.

Direct interconnects between adjacent logic elements have a shorter delay than general-purpose interconnects.

Row-based architecture

A row-based design consists of alternating rows of logic modules and programmable connecting tracks.

The rows’ outer edges are where the input-output blocks are situated. One row can be connected to adjacent rows via vertical interconnects.

There are numerous ways to join logic modules. All of the components that make up combinatorial modules are combinational. Sequential modules come with flip-flop and combinational functionalities.

This sequential module can be used to build complex combinatorial-sequential functions.

The smaller sections of the routing rails are connected with anti-fuse parts.

Hierarchical PLDs

The top level of this design is made up of interconnects and logic blocks arranged hierarchically. Every logic block has many logic modules.

There are sequential and combinatorial functional aspects in every logic module.

All these working components are under the control of the programmed memory.

Logic blocks can communicate with one another through programmable interconnect arrays. Input-output used blocks around this system of logic blocks and interconnects.

Internal Structure of an FPGA

Each FPGA includes three important features that can be found at the heart of modern-day FPGA architecture:

Logic Blocks

The logic blocks of an FPGA can be made to behave as simply as a transistor or as intricately as a microprocessor.

Numerous sequential and combinational logic functions can be implemented using it.

Different blocks, including multiplexers and dedicated memory blocks, make up modern FPGAs.

Across the logic blocks, configuration memory is employed to control the exact operation of each component. Logic blocks in an FPGA can be implemented using any of the following methods:

• Transistor pairs
• combinational gates like basic NAND gates or XOR gates
• n-input Lookup tables
• Multiplexers
• Wide fan-in And-OR structure

Routing

Routing in FPGAs is composed of variable-length wire segments connected by electrically programmable switches.

The density of logic blocks in an FPGA is determined by the length and quantity of wire segments used for routing.

The density of logic blocks used and the amount of space occupied by routing is frequently balanced by the number of connecting segments used.

Programmable routing joins logic blocks and input/output blocks to finish a user-defined design unit.

This circuit consists of tri-state buffers, pass transistors, and multiplexers. Multiplexers and pass transistors are used in a logic cluster to link the logic units.

I/O blocks

One kind of input/output device that can be used for both input and output is an input/output (I/O) block.

Input and output channels both make use of edge-triggered D flip flops.

Providing an external user interface to the FPGA’s internal architecture is the aim of the I/O blocks. On the FPGA, these cells use a large amount of space.

The significant variations in supply and reference voltages make the design of I/O programmable blocks extremely challenging.

The standard selection is important in the design of I/O architectures. Supporting a large number of standards may make I/O cells on a silicon device larger.

How does FPGA work?

FPGAs are members of the programmable logic, or programmable hardware, family of semiconductors.

Even though it is inert, an FPGA can be configured to function as almost any type of digital circuit. Nothing changes, thus this state is amazing.

The FPGA can be configured to operate like the desired circuit just by loading a configuration onto it. It is not required to solder, use jumper wires, or be hassled.

It is then possible to modify an FPGA to act like that of an additional circuit and so on. Because the arrangement is RAM-based, it may essentially be changed as often as needed. 

Even though we discuss using FPGAs to generate digital circuits, designing for them usually doesn’t involve drawing diagrams.

The complexity and size of the circuits that FPGAs could have make creating a design difficult. Alternatively, you can utilize the tools to design a circuit that emulates the desired behavior by specifying the intended behavior.

Key Differences Between FPGAs and CPLDs

Although both FPGAs and CPLDs are programmable logic devices, there are some key differences between the two architectures:

Logic Capacity

• The capacity for rationality is the most fundamental difference. Whereas CPLDs contain a few thousand to a few hundred logic gates, FPGAs have hundreds of thousands of gates, providing a far higher capacity.
• FPGAs are preferred for constructing intricate digital circuits with a high number of gates. CPLDs are appropriate for basic glue logic tasks.

Architecture and Flexibility

• Each device has a significantly distinct overall architecture and configurability. Small logic blocks are arranged in a sea atop FPGAs, coupled by an adjustable routing system. It is possible to construct extremely intricate custom architectures because of this.
• Larger macrocells are grouped in CPLDs through a basic connection network, giving the architecture a coarser overall pattern. Comparing this to FPGAs, fewer designs can be executed.

Design Entry Methods

• Hardware description languages such as VHDL or Verilog are used to set up FPGAs. This provides complete control over behavior and architecture to designers.
• Each macrocell’s function is defined by logic equations that are used to program CPLDs. Compared to design entry based on HDL, this is more limited.

Performance

• Designs requiring high memory bandwidth or a lot of parallelism can achieve substantially higher performance thanks to FPGAs’ plentiful connectivity and independent memory blocks. Algorithms for signal processing can be accelerated using certain DSP slices.
• Due to its simpler architecture, CPLD performance is more constrained than other architectures.

Cost

• For smaller logic capacity requirements, CPLDs are typically less expensive than FPGAs due to their simpler architecture. FPGAs with high densities can be highly costly.

Clock Management

• Complex clock management tiles offered by FPGAs enable several clock zones with clock skewing and frequency synthesis. For intricate synchronous digital circuits, this is helpful.
• In contrast, the clock management capabilities of CPLDs are quite limited.

Development Tools

• FPGA and CPLD design toolchains differ greatly from one another. Advanced software for design simulation, timing analysis, layout, placement & routing, and programming is available from FPGA suppliers.
• Logic compilers, which are easier to use but have less verification power, are used to program CPLDs.

Summary of Differences

Application Differences

The architectural differences between FPGAs and CPLDs make them suitable for different classes of applications:

FPGAs are ideal for:

• Compute-intensive algorithms like video processing, encryption, bioinformatics
• Complex systems requiring high data throughput and parallelism
• Advanced interfacing protocols like PCIe, Ethernet, SATA
• Prototyping ASIC/SoC designs before taping out

CPLDs are ideal for:

• Simpler glue logic, control logic, and interfacing
• Low-cost designs do not require advanced features
• Small form factor designs (CPLDs have smaller packages)

FPGA vs CPLD Example Designs

Let’s compare a few common digital systems that are constructed using FPGAs and CPLDs to further show the variations in applications appropriate for each type of programmable logic device.

FPGA Design Examples

High-Speed Network Router

A network router for high-end infrastructure has the following requirements:

• Packet forwarding at up to 400 Gbps
• Routing table lookup using TCAM
• Traffic shaping algorithms
• Buffering with high memory bandwidth
• Multiple network interfaces up to 100Gbps

To create such a high-performance router, an FPGA would be perfect. The data plane forwarding operations can be implemented using DSP slices and flexible logic blocks.

For packet buffering, large embedded memory blocks are used. High-speed interfaces like 100Gbps Ethernet are supported via the I/O blocks.

Real-Time Video Processing

A real-time video processing pipeline has the following functionality:

• Pixel processor for image enhancement
• Motion estimation for video compression
• Image pyramid generation
• Neural network-based object detection

Video processing’s highly parallel architecture is ideally suited for an FPGA. Motion estimation and pixel processing are handled by the specific DSP blocks.

Image pyramids are efficiently generated in hardware by the logic fabric implementations of the FPGA. It is also possible to map the object-detecting neural network to programmable logic.

Encryption Accelerator

An encryption accelerator card offloads processing for algorithms like AES, SHA, and RSA from the host CPU. It requires:

• High-bandwidth I/O to transfer data
• Parallel encryption engines
• Low-latency request processing

FPGAs have a performance advantage over software, which makes them popular for encryption applications.

To achieve very high throughput, the reconfigurable fabric implements parallel encryption pipelines. Comparing an FPGA to software, low-latency access to the encryption engines may also be ensured.

CPLD Design Examples

LED Controller

An LED controller drives a set of eight RGB LEDs for mood lighting based on user input. It requires:

• Debounced button inputs for mode select
• PWM generation for LED intensity control
• LED enable signals

The glue logic for the LED controller can be readily implemented by a simple CPLD with eight to sixteen macrocells.

The ability to handle parallel I/O allows for the simultaneous driving of several LEDs. PWM waveforms are produced by logic-implemented timers.

Motor Controller

An electric motor controller coordinates six motors. It requires:

• Individual speed and direction control for each motor
• Motor enable signals
• Position and speed feedback processing
• Analog voltage monitoring

A mid-size CPLD may be easily mapped to the motor controller’s glue logic and interface.

Each motor may be enabled and driven by the control signals that macrocells can produce. Further logic monitors inputs and processes feedback.

SDRAM Controller

A simple SDRAM controller interfaces to a 64MB SDRAM with a 16-bit data bus. Key requirements are:

• SDRAM command timing
• Refresh cycle generation
• Bank/row/column addressing
• Data bus buffering

Because of its parallel I/O capability and consistent timing performance, a CPLD may implement the fundamental timing and control functions required for the SDRAM controller. Nonetheless, FPGAs work better with more sophisticated memory controllers.

Choosing Between FPGAs and CPLDs

In what situations, then, is an FPGA preferable to a CPLD, and vice versa? The following criteria can be used to choose between the two categories of programmable logic:

When to Use an FPGA

• For complex logic functions requiring thousands of gates/logic cells
• If DSP capabilities like multipliers are needed
• For designs requiring lots of memory and wide memory buses
• Fast processing of parallel data is required
• Multiple high-speed serial I/O standards are required
• HDL-based design entry is preferable
• Advanced debugging capabilities are desired

When to Use a CPLD

• Only simple glue logic or interfacing is needed
• Low cost is critical
• Small packaging is required
• Low power operation is prioritized
• Simple logic equations can specify the design adequately
• Minimal debugging capabilities are sufficient

FPGAs will be the best option for the great majority of intricate, high-performance designs.

CPLDs work well in simpler glue logic applications because of their tiny form factor and inexpensive cost.

FPGA vs CPLD FAQ

Here are answers to some frequently asked questions about FPGA and CPLD differences:

Q: Can an FPGA replace a CPLD in a design?

Yes, because of its higher logic density and flexibility, an FPGA can easily accomplish the same functions as a CPLD. You might be able to increase performance and functionality by switching out a CPLD with an FPGA.

Q: Do FPGAs and CPLDs require different CAD tools?

In general, yes. Advanced toolchains for programming, place and route, synthesis, simulation, and timing analysis are offered by FPGA suppliers. With CPLDs, less complex logic compilers are used, and extensive timing analysis is not necessary.

Q: How do FPGA and CPLD programming differ?

Hardware description languages like Verilog or VHDL are used to program FPGAs. To express logic functions, Boolean equations or state machines are defined and then programmed into CPLDs.

Q: Can unused FPGA logic cells be powered down to save energy?

FPGA architectures do allow for the selective power down of parts that are not in use. When the entire FPGA gate capacity is not needed for a design, this can result in significant energy savings.

Q: Which has higher performance – FPGA or CPLD?

Because of their hard CPU cores, large memory bandwidth, DSP blocks, and plentiful routing, FPGAs perform better than other chips. The architecture of the macrocell/interconnect has limitations on CPLD performance.