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AFDX

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Avionics full-duplex switched Ethernet (AFDX) technology enables deterministic Ethernet networking for avionics and aircraft systems. The 100 Mbit/s AFDX LFT End System card supports rate-constrained traffic shaping to ensure bounded latency and jitter for deterministic Ethernet networking, as described in ARINC standards. The card can be used for production system integration and provides high-integrity redundancy management as well as an IP/UDP profiled communication layer fully implemented in hardware.

ZYNQ is an ARM SoC based FPGA from Xilinx. It includes Dual-core ARM A9 CPU, high-speed transceiver for PCIe support and 2x Tri-mode Gigabit Ethernet make it suitable candidate for AFDX implementation.

The host communicates with AFDX Card via a dedicated driver. The driver uses DMA for fast data transfers between the host and the AFDX Card. The on-board ARM processor in ZYNQ runs the AFDX protocol stack offloading the host-processors executing user applications. For efficient protocol processing, all IP/UDP are implemented in programmable logic fabric of ZYNQ. The receive and transmit buffers may be configured to operate as either sampling ports or queuing ports. A sampling port utilizes a single message buffer while a queuing port contains storage for multiple messages in a FIFO configuration.

Features

  • Integrity checking and redundancy management.
  • 1 us. Rx frame time-stamp resolution.
  • IP/UDP Offloading on hardware.
  • Profiled IP/UDP, sampled and queued ports.
  • PCI Express and DMA support.

Interfaces

  • PCI Express form factor module.
  • 2 ports 10/100 Mbit/s Ethernet.

Power Supply

  • Single +12V power supply.
  • About 7W of power consumption.

Environmental Operating Ranges

  • Operating Temp : -40oC to +80 oC
  • Humidity Level : 0 to 95%
  • Vibration Sine: 3g peak
  • Vibration random: 0.1g2 /Hz.

Specifications

Tx Virtual Channels128
Rx Virtual Channels512
Sampling/Queuing ports for Tx1024
Sampling/Queuing ports for Rx4096
Rx time-stamp resolution1 us
BAG granularity500 us. To 16 sec.

Deliverables

1AFDX End System Hardware
2Reference Design with RTL source code
3Software Drivers and Library to support AFDX Protocol.
4Test-Data
5User Manual
Support
Three Month Support Provided

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