Overview
UVM is the most widely used Verification methodology for functional verification of digital hardware (described using Verilog, System Verilog or VHDL at appropriate abstraction level).
UVM has lot of features so it’s difficult for a new user to use it efficiently. A better efficiency can be obtained by customizing the UVM base library and applying certain tips and tricks while building UVM test benches, which is mainly the purpose of this whitepaper.
In this whitepaper you will get insights on:
- Introduction
- Motivation
- What is USB Host?
- Description
- Class Codes
- USB Host Model
- Types of Host Controller
- Controllers having this feature
- Functional Description
- USB Host Flow Control
- Implementation
- Types of Packet
- Packet format
- Type of data transfer
- Token Packet Transactions
- Setup Packet
- Example : Atmel-SAMBA5D36 Host Controller
- Block Diagram
- USB Selection
- Implementation flow
- Results
- Challenges faced
- Solutions/Observations/Findings
- References
Download whitepaper
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