Join us at Embedded World Conf & Exhibition 2024 at Booth #5-350 during 9-11th April 2024

Quick Insights into PCI Gen 6 Physical Layer Logical Sub – Blocks V 0.9

The Physical Layer is present at the bottom of the PCIe hierarchy, which includes all logic functions and  circuitry for data transfer operations through the physical interface.Information, in the form of TLP and  DLLP bytes received from the Functional layer and Data Link Layer, needs to be transmitted and received  across the PCIe Express link in an appropriate serialized format at a compatible frequency supported by  the devices connected to each other across a link.

PCIe Gen6 Physical layer can transceive data at the maximum rate of 64 GT/s per lane, which is equipped  with the backward compatibility of

  • 32 GT/s,
  • 16GT/s,
  • 8GT/s,
  • 5GT/s
  • 2.5GT/s.

This layer is responsible  for the generation of Ordered Sets on the transmit side which will further be used for Link Initialization  and Training, Clock Tolerance compensation and indication for entry into and exit from low power state  on the link.

Download whitepaper

By submitting this form, I hereby agree to receive marketing information and agree with Logic Fruit Privacy Policy.

Whitepaper Overview

Get a Quote Today

By submitting this form, I hereby agree to receive marketing information and agree with Logic Fruit Privacy Policy.

or just Call us on