Nor Flash Controller
The NOR flash controller performs flash programming through SPI interface. Mainly, four operations such as read, write and erase and reset are required to program Serial NOR flash memory. The controller consists of a dedicated state machine in order to execute these operations and a SPI master which serially sends data to flash. Each FSM receive control and data signals from user interface and performs required operation.
- Single and Quad SPI interface.
- Frequency up-to 108 MHz.
- 24 bit and 32 bit addressing mode.
- Programmable SCK phase and polarity.
- Programmable device sizes.
- Supports Write Enable, Page Program, Read Data Bytes, Read Status Register, Erase Flash, Reset Flash instructions.
- Software APIs available for direct NOR Flash Read/Write.
- Easy-to-use interface with handshaking signals.
- Fully Synchronous design with single clock domain.
- Technology independent HDL Source code.
- Supports all FPGA devices.
IP Data Fact Sheet | ||||||
Configuration | Resources Utilization | Throughput @ 200 MHz | ||||
| 108 MHz, 24 bit addressing | LUTs | FFs | Block RAMs | (Mbps) | ||
| 800 | 600 | 4 | ||||
Provided with IP | ||||||
| Documents | Product Specification | |||||
| Net-list | QXP/NGD/EDIF | |||||
| Design Files | RTL-VHDL (Optional) | |||||
| Reference Design | Provided | |||||
Design Tools | ||||||
| Simulation | ModelSim SE | |||||
| Synthesis Tool | Xilinx ISE 14.4/Altera Quartus 10.1 | |||||
| Support | ||||||
| Three Month Support Provided | ||||||
