AXI Lite Interface
AXI Lite Interface has Master components, Interconnect, and Slave Components . User Logic connected to AXI-Lite Masters and AXI-Lite Slaves, and AXI-Lite Master and Slaves are connected via AXI-Lite Interconnect. All the blocks AXI-lite Master and AXI-lite Slave and AXI-Lite Interconnect blocks shown in below figure are implemented in Generic VHDL, so that it supports all FPGA devices and easily configurable.
AXI Full Interface
AXI Full Interface has Master components, Interconnect, and Slave Components . User Logic connected to AXI-Full Masters and AXI-Full Slaves, and AXI-Full Master and Slaves are connected via AXI-Full Interconnect.
- AXI Infrastructure has AXI Full and AXI Lite protocols implemented in VHDL and fully compatible with AMBA Specifications.
- AXI Full and AXI Lite Interconnect are implemented in Shared access mode (Area Optimized).
- Configurable Multiple no of master devices and slave devices , depending on resources available on FPGA.
- AXI Full and AXI Lite interconnects also Supports Read only and Write only Master devices and Slave devices resulting reduced resource utilization.
- The code is written in generic VHDL so that it can be ported to variety of FPGA’s.
- Support for multiple clock domains.
- User logic can be connected to AXI Masters and AXI Slaves with simple interface.
- Supports different interface data widths 8,16,32,64..512. And Address widths 8,16,32.
IP Data Fact Sheet
Provided with IP
|Design Files||RTL-VHDL (Optional)|
|Synthesis Tool||Xilinx ISE 14.4/Altera Quartus 10.1|
|Three Month Support Provided|