Follow us on:
If the Latency between the JESD204B interface in the FPGA and ADC Input is always fixed and constant, then we say that that the ADC is synchronized. Latency from the frame-based data input at the TX to the frame-based data output at the RX. Latency should be programmable and repeatable over power cycles and re-sync events.
Synchronization is required in many systems like Multi-antenna communications systems, Phased array radars, Magnetic resonance imaging etc. Most systems that require multiple synchronized signal chains also require synchronization of analog-to-digital converters (ADCs) and digital-to-analog converters (ADCs).