Turbo Product Code [TPC]

Turbo Product Code [TPC]

The BCH based TPC decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems.

• Fully synchronous design using a single clock
• Code block length variable from 31*31 to 127*127 symbols
• Block length can be changed at compile time
• Block length can be changed at compile time
• No of check symbols can be varied block by block in run time
• Error correcting capability (t) can be changed at runtime with condition t ≤ 2
• Automatically configured by user-entered parameters
• Provides clock enable support at input and output
• Easy-to-use interface with handshaking signals
• Supports all FPGA devices
• Maximum synthesis frequency is 200MHz
• Configurable soft input bit width with options of 4 and 5 bits
• Run time configurable error correcting capability.
• Generates decoding failure in case of uncorrectable errors with option of CRC
• Support for Extended BCH based TPC