AWGN Channel Simulator IP
- Based on Box Muller Algorithm
- Tail Accuracy of 6.6σ
- Effective Period Length of 2255
- Flat Noise Spectrum
- Supports all FPGA devices
- Maximum synthesizable frequency is 200MHZ depending on target FPGA
- Configurable input Seed value to generate different AWGN stream
- Bit Accurate MATLAB model available.
- SNR input ranges from – 30 to 50 dB
IP Data Fact Sheet | ||||
Resources Utilization | ||||
| LUTs | FFs | Block RAM | Multipliers | |
| 605 | 405 | 2 | 2 | |
Provided with IP | ||||
| Documents | Product Specification | |||
| Design Files | RTL-VHDL (Optional) | |||
| Reference Design | Provided | |||
| System Generator Model | Provided (Optional) | |||
| Matlab Bit-Accurate Model | Provided (Optional) | |||
Design Tools | ||||
| Simulation | ModelSim SE | |||
| Synthesis Tool | Xilinx ISE /Altera Quartus | |||
| Support | ||||
| Three Month Support Provided | ||||
