Video Acquisition System

The system is targeted to enhance the quality of the videos from the thermal imagers system and equip the imagers with the capability of video acquisition, video streaming and video analytics.

Video Capturing Unit and Video Processing Unit will be implemented in the PL portion of the FPGA. These units will be responsible for receiving PAL video data @ 25 fps and applying some video processing like 2D-FFT/IFFT and Bilateral/Gaussian filtering.

The raw data rate of the frames generated for PAL video @ 25 fps is 20 M-Byte/sec, Ethernet/USB cannot support such high speed. Hence, it is necessary to compress the video data before streaming it over Ethernet. We’ll use JPEG compression.

The JPEG compressed video can be either saved on board in a SD Card present on the board. The saved video will be in the form of sequence of JPAG images. The video can later be retrieved in a host PC using an USB interface.

The JPEG compressed video can be streamed over Ethernet interface to a PC. A socket connection will be created between host PC and ZYNQ board for streaming.

In both the cases of streaming and archival the frame rate may be limited due to (1) limited speed of JPEG compression running on an ARM processor on ZYNQ board, (2) limited speed of streaming over Ethernet, (3) limited speed of writing into NAND Flash/ SD Card.

Finally there will be a small application/GUI running on PC which will have a media player to display the video, also to control some of the functionalities of video streaming/archival.

The system can be broadly seen as the following simplified block diagram:

vp4

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