SPI Master/Slave Controller
- Support for both SPI Master and Slave.
- Multi Master Support.
- 8 Slave Select Lines.
- In Master Mode – bit rate generated is System Clock/2.
- In Slave Mode – bit rate supported is ≤ System Clock/8.
- Programmable SCK Phase and Polarity.
- Supports Repeated Start and Fast Read Operation.
- Transaction Layer implemented in HDL Source code as well.
- Programmable internal data path width from 1 byte to 64 bytes.
- Software APIs available for direct SPI Slave Device Register Read/Write.
- Easy-to-use interface with handshaking signals.
- Fully Synchronous design with single clock domain.
- Technology independent HDL Source code.
- Supports all FPGA devices.
- Well proven IP against multiple SPI devices.
IP Data Fact Sheet | ||||||
Configuration | Resources Utilization | Throughput @ 200 MHz | ||||
| 50 MHz 4 Byte Data Path | LUTs | FFs | Block RAMs | (Mbps) | ||
| 300 | 400 | 0 | ||||
Provided with IP | ||||||
| Documents | Product Specification | |||||
| Net-list | EDIF/QXP/NGD file | |||||
| Design Files | RTL-VHDL (Optional) | |||||
| Reference Design | Provided | |||||
Design Tools | ||||||
| Simulation | ModelSim SE | |||||
| Synthesis Tool | Xilinx ISE 14.4/Altera Quartus 10.1 | |||||
| Support | ||||||
| Three Month Support Provided | ||||||
