Job Responsibilities :

• You will develop RTL code to implement FPGA based digital designs , working from system requirements to SOC integration and design validation on HW. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines)
• Understand the system requirements and project definition
• Define architecture and detailed design spec for IP based on requirements and various trade-offs
• Micro-architecture and coding of assigned IP/design in VHDL/Verilog
• Write test bench for verifying design for complete scenario coverage
• Implementation of the design for porting on FPGA after SOC integration
• FPGA debugging and SOC integration

Requirements:

• 2+ years of experience, including successful completion of FPGA based projects
• Coding experience in VHDL and/or Verilog is must
• Experience targeting Xilinx, Lattice and/or Altera FPGAs required
• Familiarity with tools like Modelsim, Questasim/Aldec, Xilinx Vivado, Lattice Radiant, Lattice Propel is required
• Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
• Implementation of designs with multiple clock domains is required
• Thorough understanding of appropriate coding styles for FPGAs
• Completion of complete IP for FPGA based project is required
• Knowledge of basic protocols AMBA-AXI, I2C, SPI, UART is required
• Experience in one of scripting languages(i.e. TCL) will be appreciated
• Experience/knowledge in development of protocols like USB, DDRx,PCIe, Transceivers will be appreciated.

Working hours and company benefits :

• 5 days working with Flexible timing
• Group health insurance
• Free Food in office
• Get to work with industry leaders on latest technologies

If you want to apply for this position send an email to gowni.hari@logic-fruit.com with the title “Application for Sr. R&D Engineer”.