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Sr. R&D Engineer - FPGA

We are Hiring for Sr. R&D Engineer in FPGA

Job brief :

As Sr. R&D Engineer, your role will be to manage and implement complex FPGA IPs and FPGA-based digital designs.You should be able to understand the design requirements from system level requirements and define architecture/Micro architecture of IP with proper documentation.You will be helping your team for SOC development, verification, and/or debugging and SOC integration. You will be responsible for IP validation on HW.

Job Position : Sr. R&D Engineer – FPGA

Location : Gurugram/Bangalore

Reporting Manager : Business Unit Head

About Company :

At Logic Fruit, we specialize in high-quality embedded solutions and proof-of-concept (PoC) designs that require precise, supported FPGA development and real-time data generation, acquisition and analysis.

Our engineers have experience with a variety of digital protocols, communication busses, and tools including 1G, 10G Ethernet, PCIe (Gen1-Gen6), 5G, DIGRF, USB3.0, STM, HDMI, and software-defined radio (SDR), as well as encryption, protocol compliance, signal generation, data analysis, IoT technology, and multiple image processing techniques.

Some of our clients are Agilent Technologies, Keysight Technologies, BitifEye, NEC, FreeScale, Mentor Graphics, ITI, BEL and many DRDO labs, like DEAL, IRDE, LRDE, ADE, CARE and CABS. Products/Solutions developed by us are being used by BIG semiconductor companies like INTEL, STMicroElectronics, FreeScale, Sony, LG and a few more.

Job Responsibilities :

  • You will develop RTL code to implement FPGA based digital designs , working from system requirements to SOC integration and design validation on HW. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines)
  • Understand the system requirements and project definition
  • Define architecture and detailed design spec for IP based on requirements and various trade-offs
  • Micro-architecture and coding of assigned IP/design in VHDL/Verilog
  • Write test bench for verifying design for complete scenario coverage
  • Implementation of the design for porting on FPGA after SOC integration
  • FPGA debugging and SOC integration


  • 2+ years of experience, including successful completion of FPGA based projects
  • Coding experience in VHDL and/or Verilog is must
  • Experience targeting Xilinx, Lattice and/or Altera FPGAs required
  • Familiarity with tools like Modelsim, Questasim/Aldec, Xilinx Vivado, Lattice Radiant, Lattice Propel is required
  • Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
  • Implementation of designs with multiple clock domains is required
  • Thorough understanding of appropriate coding styles for FPGAs
  • Completion of complete IP for FPGA based project is required
  • Knowledge of basic protocols AMBA-AXI, I2C, SPI, UART is required
  • Experience in one of scripting languages(i.e. TCL) will be appreciated
  • Experience/knowledge in development of protocols like USB, DDRx,PCIe, Transceivers will be appreciated.

Working hours and company benefits :

  • 5 days working with Flexible timing
  • Group health insurance
  • Free Food in office
  • Get to work with industry leaders on latest technologies

If you want to apply for this position send an email to with the title “Application for Sr. R&D Engineer”.

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