Nand Flash Controller

The NAND flash controller mainly performs four operations such as memory read, write and block erase and memory reset. The controller consists of a dedicated state machine in order to execute these operations and a low level interface block which is used to generate a pulse of fixed width. Each FSM receive control and data signals from user interface and performs required operation. The flash interface consists of signals coming out from low level interface block to flash memory. The flash controller design operates at 100 MHz clock frequency and uses active high reset signal.


  • Supports up-to 64 GB of NAND Flash.
  • Programmable Page and Block size.
  • 24 bit and 32 bit addressing mode.
  • Supports Reset, Set Features, Page Program, Page Read, Block Erase instructions.
  • Software APIs available for direct NAND Flash Read/Write.
  • Easy-to-use interface with handshaking signals.
  • Fully Synchronous design with single clock domain.
  • Technology independent HDL Source code.
  • Supports all FPGA devices.
  • Well Proven IP over multiple projects.

IP Data Fact Sheet


Resources Utilization


@ 200 MHz

108 MHz, 24 bit addressing LUTs FFs Block RAMs (Mbps)
800 600 4

Provided with IP

Documents Product Specification
Design Files RTL-VHDL (Optional)
Reference Design Provided

Design Tools

Simulation ModelSim SE
Synthesis Tool Xilinx ISE 14.4/Altera Quartus 10.1
Three Month Support Provided

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