As Module Lead, your role will be to manage and  implement complex FPGA IPs and FPGA-based digital designs. You should be able to understand the project requirements and define architecture/Micro architecture with proper documentation. You will be guiding the team for system development, verification, and/or debugging  and HW/SW integration.

Requirements:

• 4+ years of experience, including successful completion of FPGA based projects
• Coding experience in VHDL and/or Verilog is must
• Experience targeting Xilinx, Lattice and/or Altera FPGAs required
• Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Lattice Radiant, Lattice Propel, Planahead, Altera Quartus etc. is required
• Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
• Implementation of designs with multiple clock domains is required
• Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
• Experience in one of high speed interfaces is required like PCIe, Ethernet, DDRx, transceivers etc.
• Experience in Timing Closure for Complex SOC will be appreciated
• Experience in RTL implementation of DSP algorithms will be appreciated
• Experience in development of USB,  ADC, DAC, AMBA-AXI, SRAM, UART, I2C, SPI will be appreciated
• Experience in one of the scripting languages(i.e.TCL) will be appreciated
• System Level Understanding of FPGA based projects will be appreciated
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