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Module Lead - FPGA

We are Hiring for FPGA Module Lead.

Job brief :

As Module Lead, your role will be to manage and  implement complex FPGA IPs and FPGA-based digital designs. You should be able to understand the project requirements and define architecture/Micro architecture with proper documentation. You will be guiding the team for system development, verification, and/or debugging  and HW/SW integration.

Job Position : Module Lead – FPGA

Location : Gurugram/Bangalore

Reporting Manager : Business Unit Head


About Company :

At Logic Fruit, we specialize in high-quality embedded solutions and proof-of-concept (PoC) designs that require precise, supported FPGA development and real-time data generation, acquisition and analysis.

Our engineers have experience with a variety of digital protocols, communication busses, and tools including 1G, 10G Ethernet, PCIe (Gen1-Gen6), 5G, DIGRF, USB3.0, STM, HDMI, and software-defined radio (SDR), as well as encryption, protocol compliance, signal generation, data analysis, IoT technology, and multiple image processing techniques.

Some of our clients are Agilent Technologies, Keysight Technologies, BitifEye, NEC, FreeScale, Mentor Graphics, ITI, BEL and many DRDO labs, like DEAL, IRDE, LRDE, ADE, CARE and CABS. Products/Solutions developed by us are being used by BIG semiconductor companies like INTEL, STMicroElectronics, FreeScale, Sony, LG and a few more.

Job Responsibilities :

  • You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines)
  • Understand the customer requirements and product definition
  • Define architecture and detailed design spec based on requirements and various trade-offs
  • Micro-architecture and coding of assigned module in VHDL/Verilog
  • Write test bench for verifying design for complete scenario coverage
  • Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement
  • FPGA debugging and HW/SW integration.


  • 4+ years of experience, including successful completion of FPGA based projects
  • Coding experience in VHDL and/or Verilog is must
  • Experience targeting Xilinx, Lattice and/or Altera FPGAs required
  • Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Lattice Radiant, Lattice Propel, Planahead, Altera Quartus etc. is required
  • Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
  • Implementation of designs with multiple clock domains is required
  • Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
  • Experience in one of high speed interfaces is required like PCIe, Ethernet, DDRx, transceivers etc.
  • Experience in Timing Closure for Complex SOC will be appreciated
  • Experience in RTL implementation of DSP algorithms will be appreciated
  • Experience in development of USB,  ADC, DAC, AMBA-AXI, SRAM, UART, I2C, SPI will be appreciated
  • Experience in one of the scripting languages(i.e.TCL) will be appreciated
  • System Level Understanding of FPGA based projects will be appreciated

Working hours and company benefits :

  • 5 days working with Flexible timing
  • Group health insurance
  • Free Food in office
  • Get to work with industry leaders on latest technologies

 If you want to apply for this position send an email to with the title “Application for Module Lead”.


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