LVDS running up to 1 Gbps line rate

LVDS interface is one of the key expertise when working with high-speed FPGA design. Some of the example where it may be required is given below

  • To provide a high speed data interfaces between two FPGAs on the board (up-to 1000 MHz)
  • To interface with high speed DAC-ADC (up-to 1 GHz)
  • For some Video interfaces e.g. Cam-link (up-to 600 MHz)
  • Between FPGA and some proprietary chip (up-to 300 MHz)

Logic-Fruit has worked on all the above type of examples. One of them is given below where a high speed LVDS interface was involved between a Virtex6 and a Kintex7 FPGA. Each LVDS channel will have 20 lines. 17 will be used for data, 1 for clock, 1 for hold, and 1 for training done signal. Hold line in LVDS channel is used to hold the data coming from another end. Training done will be in starting for calibration tap settings of IO delays of LVDS interface lines.

The overall LVDS is running at 500 MHz DDR with 8:1 SERDES modules. Thus the data to SERDES is coming at 125 MHz in the form of 8 bit interface per LVDS line. An automatic delay calibration algorithm (provided by Xilinx) was used to delay compensate multiple LVDS Lines.

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