The LDPC decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on. LDPC Codes are part of recently invented ‘Iterative decoders’, which involves multiple iterations to improve the performance. Iterative decoder shows improved performance compared to legacy convolution codes.
LDPC codes outperform Convolution codes by 3-4 dB and are characterized by a ‘water-fall’ region in their SNR – BER curve. There is a SNR threshold after which BER decreases very rapidly. Hence, LDPC codes have found their place in most of the latest standards including Wi-Fi (802.11n, 802.11ac), Wi-Max (802.16e), DVB-S2, 3GPP-LTE Advanced.
Specifications:
- Fully synchronous design using a single
- Clock
- Code Rate support of 1/2, 2/3, 3/4 and 5/6
- Block length of 648, 1256 and 1944
- Block length and Code-Rate can be changed block by block at run time
- Number of Iterations from 10 to 18 or User-defined/Automatic
- Configurable soft input bit width
- Provides clock enable support at input and output
- Easy-to-use interface with handshaking signals
- Supports all FPGA devices
- Maximum synthesizable frequency is 200MHz
- More than 100 Mbps throughput at a block size of 1944
- Decoding algorithm : Offset Min-Sum
- Message Scheduling algorithm : Layered Belief Propagation (LBP)
Enhancement Available (On Demand)
- Support for different Code-Rates/Block-Sizes
- Support for different communication standards e.g. 802.11n, 802.11ac, 802.16e, etc
- System-Generator Model and Test-Bench availability (On demand)
IP Data Fact Sheet | |||||
Configuration | Resources Utilization | Throughput @ 200 MHz | |||
Max Block Size | LUTs | FFs | Block RAMs | (Mbps) | |
2K | 48K | 23K | 61 | 70 | |
1K | 24K | 12K | 32 | 35 | |
0.5K | 12K | 6K | 20 | 20 | |
Provided with IP | |||||
Documents | Product Specification | ||||
Design Files | RTL-VHDL (Optional) | ||||
Reference Design | Provided | ||||
System Generator Model | Provided (Optional) | ||||
Matlab Bit-Accurate Model | Provided (Optional) | ||||
Design Tools | |||||
Simulation | ModelSim SE | ||||
Synthesis Tool | Xilinx ISE 14.4/Altera Quartus 10.1 | ||||
Support | |||||
Three Month Support Provided |