I2C master/slave controller

  • Support for both I2C Master and Slave.
  • Supports 100 KHz and 400 KHz mode.
  • Clock Stretching and wait state generation.
  • Supports 8 bit and 10 bit addressing mode.
  • Supports Repeated Start and Fast Read Operation.
  • Transaction Layer implemented in RTL as well.
  • Programmable register offset length, and data path width.
  • Software APIs available for direct I2C Slave Device Register Read/Write.
  • Provides clock enable support at input and output.
  • Easy-to-use interface with handshaking signals.
  • Fully Synchronous design with single clock domain.
  • Technology independent HDL Source code.
  • Supports all FPGA devices.
  • Well proven IP against multiple I2C devices.

IP Data Fact Sheet

Configuration

Resources Utilization

Throughput

@ 200 MHz

100 KHz 4 Byte Data LUTs FFs Block RAMs (Mbps)
800 600 0

Provided with IP

Documents Product Specification
Net-list EDIF/QXP/NGD file
Design Files RTL-VHDL (Optional)
Reference Design Provided

Design Tools

Simulation ModelSim SE
Synthesis Tool Xilinx ISE 14.4/Altera Quartus 10.1
Support
Three Month Support Provided

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