DDR2/3 Interface Engine
Most of high speed FPGA based project requires multiple master accessing a single DDR3 module. Some example project (which we’ve executed can be)
- Different Video Processing Algorithm IPs accessing DDR3 at the same time.
- IQ Data Streaming from Host PC to DDR memory on Card through PCIe/Ethernet interface and also streaming from DDR to multiple high-speed DAC modules.
- For testing equipment – receiving high speed multi Giga-bit real time data and storing it in real-time in DDR memory and then uploading data to Host-PC for further processing and graphical display.
- 800 MHz, 64 bit DDR modules up-to 8 GB
- Support for multiple AXI Full data-path width
- AXI Data-path Down conversion and Up conversion
- DDR band-width utilization up-to 90% of the available band-width
- Clock speed up-to 250 MHz
- Provision for different clock-rate for different Masters
- Technology independent HDL coding
We’ve designed a multi-master DDR Arbitration mechanism based on AXI-Full (AMBA) bus. An example reference design is shown below: