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LDPC Codec for CVS Applications

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Low Density Parity Check Codec for CVS Applications

  • Fully synchronous design using a single clock
  • Code Rate support of ½ and Block length support of 2K bits (coded)
  • Configurable soft input bit width
  • Very small decoding latency of the order of 10’s of us
  • Impressive BER performance (Eb/No = 2~2.5 dB @ 10-6 BER)
  • Decoding algorithm : Offset Min-Sum
  • Support of in-built bit-synchronizer for Continuous stream
  • Message Scheduling algorithm : Layered Belief Propagation (LBP).
  • Automatic insertion of synchronization sequence at Encoder side
  • Coherent bit-synchronization to keep the required SNR very low
  • Message Scheduling algorithm : Layered Belief Propagation (LBP).
  • Automatic insertion of synchronization sequence at Encoder side
  • Coherent bit-synchronization to keep the required SNR very low
  • Very low acquisition time of the order of ms
  • Support for re-acquisition
  • Very low false alarm probability
  • Provides clock enable support at input and output.
  • Supports all FPGA devices
  • Maximum synthesizable frequency is 200MHz
  • FPGA area is within 50K logic cells
  • More than 50 Mbps throughput at @ 200 MHz at Encoder output

Deliverables

DocumentsProduct Specification
Design FilesEDIF/VHDL Simulation Model
Reference DesignProvided
Source CodeProvided (Optional)
Matlab Bit-Accurate ModelProvided (Optional)

Design Tools

SimulationModelSim SE
Synthesis ToolAltera Quartus 9.1
Support
Three Month Support Provided

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