- Transform Size n = 2m, m = 5 to 16.
- Supports both FFT/IFFT operations at run-time.
- Highly optimized Radix 23 architecture.
- Output rounding modes of rounding/flooring/truncation.
- Both Pipelined and Non-Pipelined architectures are available.
- Internal bit-width are chosen so as to minimize quantization noise.
- Programmable internal data-path width of various stages.
- Decimation in Frequency (DIF) FFT algorithm.
- Input/Output in natural order.
- Input/output format – 2’s complement.
- Easy-to-use interface with handshaking signals.
- Supports all FPGA devices.
- Maximum synthesizable frequency is 200MHz.
IP Data Fact Sheet | ||||||
Configuration | Resources Utilization | Throughput @ 200 MHz | ||||
LUTs | FFs | Block RAMs | (MSps) | |||
FFT-128 | Contact Logic Fruit | 200 | ||||
FFT-256 | 200 | |||||
Provided with IP | ||||||
Documents | Product Specification | |||||
Net-list | EDIF/NGC/NGO/QXP | |||||
Design Files | RTL-VHDL (Optional) | |||||
Reference Design | Provided | |||||
System Generator Model | Provided (Optional) | |||||
Matlab Bit-Accurate Model | Provided (Optional) | |||||
Design Tools | ||||||
Simulation | ModelSim SE | |||||
Synthesis Tool | Xilinx ISE 14.4/Altera Quartus 10.1 | |||||
Support | ||||||
Three Month Support Provided |