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CORDIC

  • Supports Vector Rotation, and Angle Calculation.
  • Extended CORDIC angle range from first quadrant to the full circle.
  • Provision for amplitude compensation scaling module.
  • Output rounding modes of rounding/flooring/truncation.
  • Both Pipelined and Non-Pipelined architectures are available.
  • Programmable internal add-sub precision.
  • Programmable internal add-sub iterations.
  • Input/output format – 2’s complement.
  • Easy-to-use interface with handshaking signals.
  • Supports all FPGA devices.
  • Maximum synthesizable frequency is 200MHz.

IP Data Fact Sheet

Configuration

Resources Utilization

Throughput

@ 200 MHz

Input bit-12 Iteration-12LUTsFFsBlock RAMs(Mbps)
Pipelined130012000200
Non-Pipelined400200012

Provided with IP

DocumentsProduct Specification
Net-listEDIF/NGC/NGO/QXP
Design FilesRTL-VHDL (Optional)
Reference DesignProvided
System Generator ModelProvided (Optional)
Matlab Bit-Accurate ModelProvided (Optional)
Design Tools
SimulationModelSim SE
Synthesis ToolXilinx ISE 14.4/Altera Quartus 10.1
Support
Three Month Support Provided

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