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The BCH decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on.

  • Fully synchronous design using a single clock
  • Code block length variable from 7 to 255 symbols with up to 200 check symbols
  • Block length can be changed at compile time
  • No of check symbols can be varied block by block in run time
  • Error correcting capability (t) can be changed at runtime with condition t ≤ n/8
  • Automatically configured by user-entered parameters
  • Provides clock enable support at input and output
  • Easy-to-use interface with handshaking signals
  • Supports all FPGA devices
  • Maximum synthesizable frequency is 250MHz
  • Configurable soft input bit width
  • Run time configurable error correcting capability
  • Generates decoding failure in case of uncorrectable errors

IP Data Fact Sheet

ConfigurationResources UtilizationThroughput 
At P = 4
 
@ 60 MHz
tchannelsnLUTsFFs(Mbps)
31225512231122132
152255654668222.8
15425511993126494.8
152127609655262
7463475346383.5
7263232425142
Provided with IP 
DocumentsProduct Specification 
Design FilesRTL 
Test BenchProvided 
Octave ModelProvided 
Simulation ModelVHDL 

Design Tools

 
SimulationModelSim SE 6.4c 
Synthesis ToolXilinx ISE 14.2 
Support 
Provided by Logic Fruit Technologies 

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