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AWGN Channel Simulator IP

AWGN Channel Simulator IP

AWGN Channel Simulator IP Based on Box Muller Algorithm Tail Accuracy of 6.6σ Effective Period Length of 2255 Flat Noise Spectrum Supports all FPGA devices Maximum synthesizable frequency is 200MHZ depending on target FPGA Configurable input Seed value to generate different AWGN stream Bit Accurate MATLAB model available. SNR input ranges from – 30 to

802.11n Modem IP

802.11n Modem IP

802.11n Modem IP OFDM Modems are used in systems which are subjected to large frequency selective fading which results in inter symbol interference (ISI). By using a cyclic prefix (CP), OFDM system provides robustness against ISI. Further there is no need of complex adaptive equalizer as in single tone system. Hence, OFDM modem have found

Turbo Product Code [TPC]

Turbo Product Code

Turbo Product Code [TPC] The BCH based TPC decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems. Fully synchronous design using a single clock Code block length variable from 31*31 to 127*127 symbols Block length can be changed at compile time Block

OTN Framer and De-framer

OTN Framer and De framer

OTN Framer and De-framer To meet the increasing demand for increased bandwidth using optical fiber links, and to support 2.5 Gb, 10 Gb and 40 Gb broadband services, a new optical transport network layer was developed, the Optical Transport Network (OTN). OTN is the only standard capable of transporting 10GbE LAN PHY entirely. Different from

AFDX

AFDX

Avionics full-duplex switched Ethernet (AFDX) technology enables deterministic Ethernet networking for avionics and aircraft systems. The 100 Mbit/s AFDX LFT End System card supports rate-constrained traffic shaping to ensure bounded latency and jitter for deterministic Ethernet networking, as described in ARINC standards. The card can be used for production system integration and provides high-integrity redundancy

BCH, RS Codec

BCH RS Codec

The BCH decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on. Fully synchronous design using a single clock Code block length variable from 7 to 255 symbols with up to 200 check symbols Block length can be

TCC FEC Codec

TCC FEC Codec

The TCC is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on. TCC Codes are part of recently invented ‘Iterative decoders’, which involves multiple iterations to improve the performance. Iterative decoder shows improved performance compared to legacy convolution codes.TCC

LDPC FEC Codec

LDPC FEC Codec Thumb

The LDPC decoder is used for Forward Error Correction (FEC) in systems where transmitted data is subjected to errors before reception, e.g., communications systems, disk drives, and so on. LDPC Codes are part of recently invented ‘Iterative decoders’, which involves multiple iterations to improve the performance. Iterative decoder shows improved performance compared to legacy convolution

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